Variables for the OpenROAD Flow Scripts#

Variables are used in the OpenROAD flow to define various platform, design and tool specific variables to allow finer control and user overrides at various flow stages.

These are normally defined in the config.mk file located in the platform and design-specific directories, but can also be defined on the command line or via environment variables. For example:

Command line: make PLACE_DENSITY=0.5
Environment variable: export PLACE_DENSITY=0.5

This works provided that config.mk has defined it as a default value using the export PLACE_DENSITY?=0.4 syntax.

The actual value used is determined by the priority rules set by make:

Makefile Definitions: Variables defined in the Makefile or included files are used when they are defined using the no-override = operator, export PLACE_DENSITY=0.4 syntax. The priority within the included files is the DESIGN_CONFIG file, then Makefile definitions and finally platform(PDK) defined variables.
Command Line: Variables defined on the command line take the highest priority in overriding defaults.
Environment Variables: Variables exported in the shell environment are used if not overridden by the command line.
Default Values: Variables defined with the ?= operator in the Makefile are used only if the variable is not already defined elsewhere.

Effects of variables#

The variables for ORFS are not fully independent and can interact in complex ways. Small changes to a combination of variables can have large consequences, such as on macro placement, which can lead to vastly different quality of results.

Due to the large number of variables, some of which are continuous and require long runtimes, other discrete, it is not feasible to perform an exhaustive end-to-end search for the best combination of variables.

Instead, the following approaches are used to determine reasonable values, up to a point of diminishing returns:

Experience: Leveraging domain expertise to set initial values.
AI: Using machine learning techniques to explore variable combinations.
Parameter Sweeps: Testing a smaller subset of variables to identify optimal ranges.

These values are then set in configuration files and kept under source control alongside the RTL input.

Types of variables#

Variables values are set in ORFS scripts or config.mk files and are kept in source control together with configuration files and RTL.

It is an ongoing effort to move variables upwards in the categories below.

Category	Definition	User Involvement	Examples	Automation Potential	Notes
Trivial	Automatically determined by tool with near-optimal results.	None (unless debugging)	Buffer sizing, default layers	High – can be hidden	Best if invisible; surfaced only in debug or verbose mode.
Easy	Requires input, but easy to tune using reports or visuals.	Moderate – copy/edit from reports	`PLACE_DENSITY`	Medium–High	Smooth response curves, intuitive tuning.
Complex	Small changes in values may result in large effects.	High – requires multiple runs/sweeps	`CTS_DISTANCE_BUF`, small changes can have large effects on skew and quality of results. Small changes to independent inputs, such as RTL, can invalidate earlier “good values”.	Low–Medium	Needs scripted sweeps and statistical evaluation.

Platform#

These variables must be defined in the platform specific config file located in the OpenROAD-flow-scripts directory of ./flow/platforms/<PLATFORM>/config.mk

Note: The variable PLATFORM_DIR is set by default based on the PLATFORM variable. For OpenROAD Flow Scripts we have the following public platforms:

sky130hd
sky130hs
nangate45
asap7

Platform Specific Variables#

The table below lists the complete set of variables used in each of the public platforms supported by the OpenROAD flow.

Note:

= indicates default definition assigned by the tool
?= indicates that the variable value may be reassigned with design config.mk

Design Specific Configuration Variables#

Required Variables#

Required variables must be defined in the design configuration file for each design located in the OpenROAD-flow-scripts directory of ./flow/designs/<PLATFORM>/<DESIGN_NAME>/config.mk

Optional Variables#

These are optional variables that may be over-ridden/appended with default value from the platform config.mk by defining in the design configuration file.

Automatically generated tables from flow/scripts/variables.yaml#

Variables in alphabetic order#

Variable	Description	Default
ABC_AREA	Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.	0
ABC_CLOCK_PERIOD_IN_PS	Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.
ABC_DRIVER_CELL	Default driver cell used during ABC synthesis.
ABC_LOAD_IN_FF	During synthesis set_load value used.
ABSTRACT_SOURCE	Which .odb file to use to create abstract
ADDER_MAP_FILE	Optional mapping file supplied to Yosys to map adders
ADDITIONAL_FILES	Additional files to be added to `make issue` archive.
ADDITIONAL_GDS	Hardened macro GDS files listed here.
ADDITIONAL_LEFS	Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.
ADDITIONAL_LIBS	Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.
ADDITIONAL_SITES	Passed as -additional_sites to initialize_floorplan.
ASAP7_USE_VT	A space separated list of VT options to use with the ASAP7 standard cell library: RVT, LVT, SLVT.	RVT
BALANCE_ROWS	Balance rows during placement.	0
BLOCKS	Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.
BUFFER_PORTS_ARGS	Specify arguments to the buffer_ports call during placement. Only used if DONT_BUFFER_PORTS=0.
CACHED_REPORTS	List of pre-existing report files to copy into the reports directory before synthesis. Used when reusing prior synthesis results with SYNTH_NETLIST_FILES.
CAP_MARGIN	Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.
CDL_FILE	CDL master netlist file used as the -masters argument to write_cdl for generating Circuit Description Language output.
CDL_FILES	Insert additional Circuit Description Language (`.cdl`) netlist files.
CELL_PAD_IN_SITES_DETAIL_PLACEMENT	Cell padding on both sides in site widths to ease routability in detail placement.	0
CELL_PAD_IN_SITES_GLOBAL_PLACEMENT	Cell padding on both sides in site widths to ease routability during global placement.	0
CLKGATE_MAP_FILE	Optional mapping file supplied to Yosys to map clock gating cells
CLUSTER_FLOPS	Enable clustering of flip-flops into multi-bit flip-flops, if the platform PDK includes multi-bit flip-flops	0
CLUSTER_FLOPS_ARGS	Additional arguments passed to the cluster_flops command. Only used when CLUSTER_FLOPS is set.
CORE_AREA	The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).
CORE_ASPECT_RATIO	The core aspect ratio (height / width). This variable is only used when `CORE_UTILIZATION` is set.	1.0
CORE_MARGIN	The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is only used when `CORE_UTILIZATION` is set.	1.0
CORE_UTILIZATION	The core utilization percentage (0-100).
CORNER	PVT corner library selection. Only available for ASAP7 and GF180 PDKs.
CORNERS	List of timing corner names for multi-corner analysis (e.g. “slow fast”). When set, liberty files are loaded per corner using uppercase _LIB_FILES environment variables (e.g. corner “slow” reads SLOW_LIB_FILES) and timing models are generated per corner.
CTS_ARGS	Override `clock_tree_synthesis` arguments.
CTS_BUF_DISTANCE	Distance (in microns) between buffers.
CTS_BUF_LIST	List of cells used to construct the clock tree. Overrides buffer inference.
CTS_CLUSTER_DIAMETER	Maximum diameter (in microns) of sink cluster.
CTS_CLUSTER_SIZE	Maximum number of sinks per cluster.
CTS_LIB_NAME	Name of the Liberty library to use in selecting the clock buffers.
CTS_SNAPSHOT	Creates ODB/SDC files prior to clock net and setup/hold repair.
CTS_SNAPSHOTS	Create ODB/SDC files at different stages of CTS.	0
DESIGN_NAME	The name of the top-level module of the design.
DESIGN_NICKNAME	DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.
DETAILED_METRICS	If set, then calls report_metrics prior to repair operations in the CTS and global route stages	0
DETAILED_ROUTE_ARGS	Add additional arguments for debugging purposes during detail route.
DETAILED_ROUTE_END_ITERATION	Maximum number of iterations.	64
DETAIL_PLACEMENT_ARGS	Specify arguments to the detailed_placement call during placement.
DFF_LIB_FILE	Single Liberty file for flip-flop technology mapping (dfflibmap) during synthesis. Takes precedence over DFF_MAP_FILE when set.
DFF_MAP_FILE	Optional mapping file supplied to Yosys to map D flip-flops
DIE_AREA	The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).
DISABLE_VIA_GEN	Passed as -disable_via_gen to detailed_route.
DONT_BUFFER_PORTS	Do not buffer input/output ports during floorplanning.	0
DONT_USE_CELLS	Dont use cells eases pin access in detailed routing.
DPO_MAX_DISPLACEMENT	Specifies how far an instance can be moved when optimizing.	5 1
EARLY_SIZING_CAP_RATIO	Ratio between the input pin capacitance and the output pin load during initial gate sizing.
ENABLE_DPO	Enable detail placement with improve_placement feature.	1
ENABLE_PLACE_REPAIR_TIMING	Run repair_timing during the placement resize stage using placement parasitics. Disabled by default; pre-CTS setup/hold repair is skipped unless this is set to 1.	0
ENABLE_RESISTANCE_AWARE	Passed as -resistance_aware to global_route.
FASTROUTE_TCL	Specifies a Tcl script with commands to run before FastRoute.
FILL_CELLS	Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.
FILL_CONFIG	JSON rule file for metal fill during chip finishing.
FLOORPLAN_DEF	Use the DEF file to initialize floorplan. Mutually exclusive with FOOTPRINT or DIE_AREA/CORE_AREA or CORE_UTILIZATION.
FLOW_VARIANT	Flow variant to use, used in the flow variant directory name.	base
FOOTPRINT	Custom footprint definition file for ICeWall-based floorplan initialization. Mutually exclusive with FLOORPLAN_DEF or DIE_AREA/CORE_AREA or CORE_UTILIZATION.
FOOTPRINT_TCL	Specifies a Tcl script with custom footprint-related commands for floorplan setup.
GDS_ALLOW_EMPTY	Single regular expression of module names of macros that have no .gds file
GDS_FILES	Path to platform GDS files.
GENERATE_ARTIFACTS_ON_FAILURE	For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren’t covered by the “useful to inspect the artifacts on failure” use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.	0
GLOBAL_PLACEMENT_ARGS	Use additional tuning parameters during global placement other than default args defined in global_place.tcl.
GLOBAL_ROUTE_ARGS	Replaces default arguments for global route.	-congestion_iterations 30 -congestion_report_iter_step 5 -verbose
GND_NETS_VOLTAGES	Used for IR Drop calculation.
GPL_KEEP_OVERFLOW	Passed as -keep_resize_below_overflow to global_placement. Only used when GPL_TIMING_DRIVEN is enabled.
GPL_ROUTABILITY_DRIVEN	Specifies whether the placer should use routability driven placement.	1
GPL_TIMING_DRIVEN	Specifies whether the placer should use timing driven placement.	1
GUI_TIMING	Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.	1
HOLD_SLACK_MARGIN	Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design’s target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.	0
IO_CONSTRAINTS	File path to the IO constraints .tcl file. Also used for manual placement.
IO_PLACER_H	A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die).
IO_PLACER_V	A list of metal layers on which the I/O pins are placed vertically (sides of the die).
IR_DROP_LAYER	Default metal layer to report IR drop.
KEEP_VARS	Feature toggle to keep intermediate variables during the flow. This is useful for the single-run flow, where all stages of the flow are run in a single OpenROAD instance.	0
KLAYOUT_TECH_FILE	A mapping from LEF/DEF to GDS using the KLayout tool.
LATCH_MAP_FILE	Optional mapping file supplied to Yosys to map latches
LAYER_PARASITICS_FILE	Path to per layer parasitics file. Defaults to $(PLATFORM_DIR)/setRC.tcl.
LEC_AUX_VERILOG_FILES	Additional Verilog files (e.g. blackbox stubs) to include in LEC equivalence checks. Appended to the generated Verilog netlist before running the formal equivalence check.
LEC_CHECK	Perform a formal equivalence check between before and after netlists. If this fails, report an issue to OpenROAD.	0
LIB_FILES	A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.
LIB_MODEL	Selects between NLDM and CCS timing models for the ASAP7 platform. Valid values: NLDM (default), CCS. Used in flow/platforms/asap7/config.mk to pick the LIB_DIR subdirectory and accumulate the corresponding $(CORNER)_$(LIB_MODEL)_LIB_FILES list, and in flow/scripts/load.tcl to gate CCS-specific Tcl branches.	NLDM
MACRO_BLOCKAGE_HALO	Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.
MACRO_EXTENSION	Sets the number of GCells added to the blockages boundaries from macros.
MACRO_PLACEMENT_TCL	Specifies the path of a TCL file on how to place macros manually. The user may choose to place just some of the macros in the design. The macro placer will handle the remaining unplaced macros.
MACRO_PLACE_HALO	Horizontal/vertical halo around macros (microns). Used by automatic macro placement.
MACRO_ROWS_HALO_X	Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.
MACRO_ROWS_HALO_Y	Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.
MACRO_WRAPPERS	The wrapper file that replaces existing macros with their wrapped version.
MAKE_TRACKS	Tcl file that defines add routing tracks to a floorplan.
MATCH_CELL_FOOTPRINT	Enforce sizing operations to only swap cells that have the same layout boundary.	0
MAX_PLACE_STEP_COEF	Sets the maximum phi coefficient (pcof_max / µ_k Upper Bound) for global placement optimization. This parameter controls the step size upper bound in the RePlAce Nesterov optimization algorithm. Higher values allow more aggressive optimization but may risk divergence. Valid range: 1.00-1.20	1.05
MAX_REPAIR_ANTENNAS_ITER_DRT	Defines the maximum number of iterations post-detailed routing repair antennas will run.	5
MAX_REPAIR_ANTENNAS_ITER_GRT	Defines the maximum number of iterations post global routing repair antennas will run.	5
MAX_REPAIR_TIMING_ITER	Maximum number of iterations for repair setup and repair hold.
MAX_ROUTING_LAYER	The highest metal layer name to be used in routing.
MIN_BUF_CELL_AND_PORTS	Used to insert a buffer cell to pass through wires. Used in synthesis.
MIN_CLK_ROUTING_LAYER	The lowest metal layer name to be used for clock-net routing in global routing. Used in flow/platforms/*/fastroute.tcl as the lower bound of `set_routing_layers -clock`. Typically higher than MIN_ROUTING_LAYER so clock nets prefer the upper, lower-RC layers. No `stages:` list because floorplan.tcl also `source`s the platform fastroute.tcl.
MIN_PLACE_STEP_COEF	Sets the minimum phi coefficient (pcof_min / µ_k Lower Bound) for global placement optimization. This parameter controls the step size lower bound in the RePlAce Nesterov optimization algorithm. Lower values may improve convergence but can increase runtime. Valid range: 0.95-1.05	0.95
MIN_ROUTING_LAYER	The lowest metal layer name to be used in routing.
NUM_CORES	Passed to `openroad -threads $(NUM_CORES)`, defaults to numbers of cores in system as determined by system specific code in Makefile, `nproc` is tried first. OpenROAD does not limit itself to this number of cores across OpenROAD running instances, which can lead to overprovisioning in contexts such as bazel-orfs where there could be many routing, or place jobs running at the same time.
OPENROAD_HIERARCHICAL	Feature toggle to enable to run OpenROAD in hierarchical mode, otherwise considered flat. Will eventually be the default and this option will be retired.	0
OR_K	Passed as -or_k to detailed routing.
OR_SEED	Passed as -or_seed to detailed routing.
PDN_TCL	File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.
PLACE_DENSITY	The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. The default is platform specific.
PLACE_DENSITY_LB_ADDON	Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.
PLACE_PINS_ARGS	Arguments to place_pins
PLACE_SITE	Placement site for core cells defined in the technology LEF file.
PLATFORM	Specifies process design kit or technology node to be used.
PLATFORM_TCL	Specifies a Tcl script with commands to run before loading design.
POST_CTS_TCL	Specifies a Tcl script with commands to run after CTS is completed.
POST_DENSITY_FILL_TCL	Specifies a Tcl script with commands to run after density fill.
POST_DETAIL_PLACE_TCL	Specifies a Tcl script with commands to run after detailed placement.
POST_DETAIL_ROUTE_TCL	Specifies a Tcl script with commands to run after detailed route.
POST_FILLCELL_TCL	Specifies a Tcl script with commands to run after fillcell insertion.
POST_FINAL_REPORT_TCL	Specifies a Tcl script with commands to run after final report generation.
POST_FLOORPLAN_TCL	Specifies a Tcl script with commands to run after floorplan is completed.
POST_GLOBAL_PLACE_SKIP_IO_TCL	Specifies a Tcl script with commands to run after global placement (skip IO).
POST_GLOBAL_PLACE_TCL	Specifies a Tcl script with commands to run after global placement.
POST_GLOBAL_ROUTE_TCL	Specifies a Tcl script with commands to run after global route.
POST_IO_PLACEMENT_TCL	Specifies a Tcl script with commands to run after IO placement.
POST_MACRO_PLACE_TCL	Specifies a Tcl script with commands to run after macro placement.
POST_PDN_TCL	Specifies a Tcl script with commands to run after PDN generation.
POST_RESIZE_TCL	Specifies a Tcl script with commands to run after resize.
POST_SYNTH_TCL	Specifies a Tcl script with commands to run after synthesis ODB generation.
POST_TAPCELL_TCL	Specifies a Tcl script with commands to run after tapcell.
PRE_CTS_TCL	Specifies a Tcl script with commands to run before CTS.
PRE_DENSITY_FILL_TCL	Specifies a Tcl script with commands to run before density fill.
PRE_DETAIL_PLACE_TCL	Specifies a Tcl script with commands to run before detailed placement.
PRE_DETAIL_ROUTE_TCL	Specifies a Tcl script with commands to run before detailed route.
PRE_FILLCELL_TCL	Specifies a Tcl script with commands to run before fillcell insertion.
PRE_FINAL_REPORT_TCL	Specifies a Tcl script with commands to run before final report generation.
PRE_FLOORPLAN_TCL	Specifies a Tcl script with commands to run before floorplan.
PRE_GLOBAL_PLACE_SKIP_IO_TCL	Specifies a Tcl script with commands to run before global placement (skip IO).
PRE_GLOBAL_PLACE_TCL	Specifies a Tcl script with commands to run before global placement.
PRE_GLOBAL_ROUTE_TCL	Specifies a Tcl script with commands to run before global route.
PRE_IO_PLACEMENT_TCL	Specifies a Tcl script with commands to run before IO placement.
PRE_MACRO_PLACE_TCL	Specifies a Tcl script with commands to run before macro placement.
PRE_PDN_TCL	Specifies a Tcl script with commands to run before PDN generation.
PRE_RESIZE_TCL	Specifies a Tcl script with commands to run before resize.
PRE_SYNTH_TCL	Specifies a Tcl script with commands to run before synthesis ODB generation.
PRE_TAPCELL_TCL	Specifies a Tcl script with commands to run before tapcell.
PROCESS	Technology node or process in use.
PWR_NETS_VOLTAGES	Used for IR Drop calculation.
RCX_RULES	RC Extraction rules file path.
RECOVER_POWER	Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].	0
REMOVE_ABC_BUFFERS (deprecated)	Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.	0
REMOVE_CELLS_FOR_LEC	String patterns directly passed to write_verilog -remove_cells <> for lec checks.
REPAIR_PDN_VIA_LAYER	Remove power grid vias which generate DRC violations after detailed routing.
REPORT_CLOCK_SKEW	Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.	1
ROUTING_LAYER_ADJUSTMENT	Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/whittle.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. whittle.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.	0.5
RTLMP_AREA_WT	Weight for the area of the current floorplan.	0.1
RTLMP_ARGS	Overrides all other RTL macro placer arguments.
RTLMP_BOUNDARY_WT	Weight for the boundary or how far the hard macro clusters are from boundaries.	50.0
RTLMP_FENCE_LX	Defines the lower left X coordinate for the global fence bounding box in microns.	0.0
RTLMP_FENCE_LY	Defines the lower left Y coordinate for the global fence bounding box in microns.	0.0
RTLMP_FENCE_UX	Defines the upper right X coordinate for the global fence bounding box in microns.	0.0
RTLMP_FENCE_UY	Defines the upper right Y coordinate for the global fence bounding box in microns.	0.0
RTLMP_MAX_INST	Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.
RTLMP_MAX_LEVEL	Maximum depth of the physical hierarchy tree.	2
RTLMP_MAX_MACRO	Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.
RTLMP_MIN_AR	Specifies the minimum aspect ratio (height/width).	0.33
RTLMP_MIN_INST	Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.
RTLMP_MIN_MACRO	Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.
RTLMP_NOTCH_WT	Weight for the notch, or the existence of dead space that cannot be used for placement and routing.	50.0
RTLMP_OUTLINE_WT	Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.	100.0
RTLMP_RPT_DIR	Path to the directory where reports are saved.
RTLMP_WIRELENGTH_WT	Weight for half-perimiter wirelength.	100.0
RULES_JSON	json files with the metrics baseline regression rules. In the ORFS Makefile, this defaults to $DESIGN_DIR/rules-base.json, but ORFS does not mandate the users source directory layout and this can be placed elsewhere when the user sets up an ORFS config.mk or from bazel-orfs.
RUN_LOG_NAME_STEM	Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.	run
RUN_SCRIPT	Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.
SC_LEF	Path to technology standard cell LEF file.
SDC_FILE	The path to design constraint (SDC) file.
SDC_GUT	Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.
SEAL_GDS	Seal macro to place around the design.
SETUP_MOVE_SEQUENCE	Passed as -sequence to repair_timing. This should be a string of move keywords separated by commas.
SETUP_SLACK_MARGIN	Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.	0
SET_RC_TCL	Metal & Via RC definition file path.
SKIP_ANTENNA_REPAIR	Skips antenna repair entirely.	0
SKIP_ANTENNA_REPAIR_POST_DRT	Skips antenna repair post-detailed routing.	0
SKIP_ANTENNA_REPAIR_PRE_GRT	Skips antenna repair pre-global routing.	0
SKIP_BUFFER_REMOVAL	Passed as -skip_buffer_removal to repair_timing. Do not remove buffers as a transform to fix timing violations (default: allow buffer removal).
SKIP_CRIT_VT_SWAP	Do not perform VT swap on critical cells to improve QoR (default: do critical VT swap). This is an additional VT swap on critical cells that remain near the end of setup fixing. If SKIP_VT_SWAP is set to 1, this also disables critical cell VT swap.
SKIP_CTS_REPAIR_TIMING	Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.	0
SKIP_DETAILED_ROUTE	Skips detailed route.	0
SKIP_GATE_CLONING	Do not use gate cloning transform to fix timing violations (default: use gate cloning).
SKIP_INCREMENTAL_REPAIR	Skip incremental repair in global route.	0
SKIP_LAST_GASP	Do not use last gasp optimization to fix timing violations (default: use gate last gasp).
SKIP_PIN_SWAP	Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).
SKIP_REPAIR_TIE_FANOUT	Skip repair_tie_fanout at floorplan step.	0
SKIP_REPORT_METRICS	If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.	0
SKIP_VT_SWAP	Do not perform VT swap to improve QoR (default: do VT swap).
SLANG_PLUGIN_PATH	Path to the slang plugin for Yosys. This can be a full path to a custom-built plugin (e.g. for Bazel builds) or just the plugin name.	slang
SLEW_MARGIN	Specifies a slew margin when fixing max slew violations. This option allows you to overfix.
SWAP_ARITH_OPERATORS	Improve timing QoR by swapping ALU and MULT arithmetic operators.
SYNTH_ARGS	Optional synthesis variables for yosys.
SYNTH_BLACKBOXES	List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design. Non-existant modules are ignored silently, useful when listing modules statically, even if modules come and go dynamically.
SYNTH_CANONICALIZE_TCL	Specifies a Tcl script with commands to run as part of the synth canonicalize step.
SYNTH_CHECKPOINT	Path to a Yosys RTLIL checkpoint to read in place of the default canonicalization checkpoint at the start of synth.tcl. Intended for parallel synthesis flows that reuse a checkpoint taken after coarse synthesis and `keep_hierarchy` have already been decided, so each partition skips that common prefix. Leave unset for the normal flow.
SYNTH_GUT	Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.	0
SYNTH_HDL_FRONTEND	Select an alternative language frontend to ingest the design. Available option is “slang”. If the variable is empty, design is read with the Yosys read_verilog command.
SYNTH_HIERARCHICAL	Enable to Synthesis hierarchically, otherwise considered flat synthesis.	0
SYNTH_HIER_SEPARATOR	Separator used for the synthesis flatten stage.	.
SYNTH_INSBUF	Insert input buffers on top-level input ports during synthesis. Useful to disable when doing parallel synthesis and concatenating netlists later as we’re generating netlists of submodules.	1
SYNTH_KEEP_MOCKED_MEMORIES	When `SYNTH_MOCK_LARGE_MEMORIES=1`, setting this to 1, will keep mocked memories (not flattening them). This preserves some of the access logic complexity and avoids optimizations outside of the mocked memory.	1
SYNTH_KEEP_MODULES	Mark modules to keep from getting removed in flattening.
SYNTH_MEMORY_MAX_BITS	Maximum number of bits for memory synthesis. Ideally, real RAM or realistic fakeram should be used for RAMs much larger than 1024 bits. To temporarily ignore the RAM concerns and investigate other aspects of the design, consider setting `SYNTH_MOCK_LARGE_MEMORIES=1`, or adjusting `SYNTH_MEMORY_MAX_BITS`.	4096
SYNTH_MINIMUM_KEEP_SIZE	For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform’s standard cell library. The default value is platform specific.	0
SYNTH_MOCK_LARGE_MEMORIES	Reduce Yosys inferred memories larger than SYNTH_MEMORY_MAX_BITS to 1 row. Yosys will generally infer memories from behavioral Verilog code, whether the memories are in standalone modules or instantiated within some larger module. fakeram and empty Verilog memories(blackboxes) of memories will not be inferred memories by Yosys and are therefore not affected by this variable. This is useful and convenient to separate the concern of instantiating and placing memories from investigating other issues with a design, though it comes at the expense of the increased accuracy that using realistic fakemem would provide. Memories with a single 1 row will of course have unrealistically good timing and area characteristics, but timing will still correctly terminate in a register. Large port memories, typically register files, will still have the retain a lot of the port logic that can be useful to investigate issues. This can be especially useful during development of designs where the behavioral model comes first and suitable memories are matched up when the design RTL is stable. A typical use case would be Chisel which will generate a behavioral model for a memories with the required clocks, ports, etc. in addition to a computer readable file with the specification of the memories that is used to automatically match up suitable memory macros later in the flow. During an architectural screening study, a large range of memory configurations can be investigated quickly with this option, without getting bogged down in the concern of how to realize the memories in silicon for emphemral RTL configurations that exist only long enough to run through the ORFS flow to create a table of some characteristics of a design configuration.	0
SYNTH_NETLIST_FILES	Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.
SYNTH_OPERATIONS_ARGS	Extra arguments appended to the Yosys synth command operations list. When set, replaces the default Kogge-Stone adder extra-map.
SYNTH_OPT_HIER	Optimize constants across hierarchical boundaries.
SYNTH_REPEATABLE_BUILD	License to prune anything that makes builds less repeatable, typically used with Bazel to ensure that builds are bit-for-bit identical so that caching works optimally. Removes debug information that encodes paths, timestamps, etc.	0
SYNTH_RETIME_MODULES	This is an experimental option and may cause adverse effects. No effort has been made to check if the retimed RTL is logically equivalent to the non-retimed RTL. List of modules to apply automatic retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. The main use case is to quickly identify if performance can be improved by manually retiming the input RTL. Retiming will treat module ports like register endpoints/startpoints. The objective function of retiming isn’t informed by SDC, even the clock period is ignored. As such, retiming will optimize for best delay at potentially high register number cost. Automatic retiming can produce suboptimal results as its timing model is crude and it doesn’t find the optimal distribution of registers on long pipelines. See OR discussion # 8080.
SYNTH_SKIP_KEEP	Only meaningful together with SYNTH_CHECKPOINT. When set, signals that the supplied checkpoint is still canonical RTLIL (coarse synth and `keep_hierarchy` have not been run yet), so synth.tcl runs the full coarse+fine synthesis flattened. When unset and SYNTH_CHECKPOINT is used, synth.tcl assumes the checkpoint already has coarse synth + `keep_hierarchy` done and resumes from `coarse:fine`.	0
SYNTH_SLANG_ARGS	Additional arguments passed to the slang frontend during synthesis.
SYNTH_USE_SYN	If set to 1, run synthesis using the “syn” tool built into OpenROAD (the synth_syn.tcl flow) instead of the default Yosys-based flow. Defaults to 0 (Yosys flow).	0
SYNTH_WRAPPED_ADDERS	Specify the adder modules that can be used for synthesis, separated by commas. The default adder module is determined by the first element of this variable.
SYNTH_WRAPPED_MULTIPLIERS	Specify the multiplier modules that can be used for synthesis, separated by commas. The default multiplier module is determined by the first element of this variable.
SYNTH_WRAPPED_OPERATORS	Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.
TAPCELL_TCL	Path to Endcap and Welltie cells file.
TAP_CELL_NAME	Name of the cell to use in tap cell insertion.
TECH_LEF	A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.
TIEHI_CELL_AND_PORT	Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.
TIELO_CELL_AND_PORT	Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.
TIE_SEPARATION	Distance separating tie high/low instances from the load.	0
TNS_END_PERCENT	Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.	100
UNSET_ABC9_BOX_CELLS	List of cells to unset the abc9_box attribute on
USE_FILL	Whether to perform metal density filling.	0
USE_NEGOTIATION	Enable using negotiation legalizer for detailed placement.	0
VERILOG_DEFINES	Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`
VERILOG_FILES	The path to the design Verilog/SystemVerilog files providing a description of modules.
VERILOG_INCLUDE_DIRS	Specifies the include directories for the Verilog input files.
VERILOG_TOP_PARAMS	Apply toplevel params (if exist). Passed in as a list of key value pairs in tcl syntax; separated by spaces: PARAM1 VALUE1 PARAM2 VALUE2
VIA_IN_PIN_MAX_LAYER	Passed as -via_in_pin_top_layer to pin_access and detailed_route.
VIA_IN_PIN_MIN_LAYER	Passed as -via_in_pin_bottom_layer to pin_access and detailed_route.
WRITE_ODB_AND_SDC_EACH_STAGE	Save out .sdc and .odb file after each stage, useful to disable when using a single OpenROAD instance to run all stages of the flow.	1
YOSYS_FLAGS	Flags to pass to yosys.	-v 3