Environment Variables for the OpenROAD Flow Scripts#

Environment variables are used in the OpenROAD flow to define various platform, design and tool specific variables to allow finer control and user overrides at various flow stages. These are defined in the config.mk file located in the platform and design specific directories.

Platform#

These variables must be defined in the platform specific config file located in the OpenROAD-flow-scripts directory of ./flow/platforms/<PLATFORM>/config.mk

Note: The variable PLATFORM_DIR is set by default based on the PLATFORM variable. For OpenROAD Flow Scripts we have the following public platforms:

sky130hd
sky130hs
nangate45
asap7

Platform Specific Environment Variables#

The table below lists the complete set of variables used in each of the public platforms supported by the OpenROAD flow.

Note:

= indicates default definition assigned by the tool
?= indicates that the variable value may be reassigned with design config.mk

Design Specific Configuration Variables#

Required Variables#

Required variables must be defined in the design configuration file for each design located in the OpenROAD-flow-scripts directory of ./flow/designs/<PLATFORM>/<DESIGN_NAME>/config.mk

Optional Variables#

These are optional variables that may be over-ridden/appended with default value from the platform config.mk by defining in the design configuration file.

Automatically generated tables from flow/scripts/variables.yaml#

Variables in alphabetic order#

Variable	Description	Default	Deprecated
ABC_AREA	Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.	0
ABC_CLOCK_PERIOD_IN_PS	Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.
ABC_DRIVER_CELL	Default driver cell used during ABC synthesis.
ABC_LOAD_IN_FF	During synthesis set_load value used.
ABSTRACT_SOURCE	Which .odb file to use to create abstract
ADDER_MAP_FILE	List of adders treated as a black box by Yosys.
ADDITIONAL_FILES	Additional files to be added to `make issue` archive.
ADDITIONAL_GDS	Hardened macro GDS files listed here.
ADDITIONAL_LEFS	Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.
ADDITIONAL_LIBS	Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.
BLOCKS	Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.
CAP_MARGIN	Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.
CDL_FILES	Insert additional Circuit Description Language (`.cdl`) netlist files.
CELL_PAD_IN_SITES_DETAIL_PLACEMENT	Cell padding on both sides in site widths to ease routability in detail placement.	0
CELL_PAD_IN_SITES_GLOBAL_PLACEMENT	Cell padding on both sides in site widths to ease routability during global placement.	0
CLKGATE_MAP_FILE	List of cells for gating clock treated as a black box by Yosys.
CORE_AREA	The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).
CORE_ASPECT_RATIO	The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.
CORE_MARGIN	The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.
CORE_UTILIZATION	The core utilization percentage (0-100).
CORNER	PVT corner library selection. Only available for ASAP7 and GF180 PDKs.
CTS_ARGS	Override `clock_tree_synthesis` arguments.
CTS_BUF_DISTANCE	Distance (in microns) between buffers.
CTS_CLUSTER_DIAMETER	Maximum diameter (in microns) of sink cluster.	20
CTS_CLUSTER_SIZE	Maximum number of sinks per cluster.	50
CTS_SNAPSHOT	Creates ODB/SDC files prior to clock net and setup/hold repair.
DESIGN_NAME	The name of the top-level module of the design.
DESIGN_NICKNAME	DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.
DETAILED_METRICS	If set, then calls report_metrics prior to repair operations in the CTS and global route stages	0
DETAILED_ROUTE_ARGS	Add additional arguments for debugging purposes during detail route.
DETAILED_ROUTE_END_ITERATION	Maximum number of iterations.	64
DFF_LIB_FILES	Technology mapping liberty files for flip-flops.
DIE_AREA	The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).
DONT_USE_CELLS	Dont use cells eases pin access in detailed routing.
DONT_USE_LIBS	Set liberty files as `dont_use`.
DPO_MAX_DISPLACEMENT	Specifies how far an instance can be moved when optimizing.	5 1
ENABLE_DPO	Enable detail placement with improve_placement feature.	1
EQUIVALENCE_CHECK	Enable running equivalence checks to verify logical correctness of repair_timing.	0
FASTROUTE_TCL	Specifies a Tcl script with commands to run before FastRoute.
FILL_CELLS	Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.
FILL_CONFIG	JSON rule file for metal fill during chip finishing.
FLOORPLAN_DEF	Use the DEF file to initialize floorplan.
FLOW_VARIANT	Flow variant to use, used in the flow variant directory name.	base
GDS_ALLOW_EMPTY	Regular expression of module names of macros that have no .gds file
GDS_FILES	Path to platform GDS files.
GENERATE_ARTIFACTS_ON_FAILURE	For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren’t covered by the “useful to inspect the artifacts on failure” use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.	0
GLOBAL_PLACEMENT_ARGS	Use additional tuning parameters during global placement other than default args defined in global_place.tcl.
GLOBAL_ROUTE_ARGS	Replaces default arguments for global route.	-congestion_iterations 30 -congestion_report_iter_step 5 -verbose
GND_NETS_VOLTAGES	Used for IR Drop calculation.
GPL_ROUTABILITY_DRIVEN	Specifies whether the placer should use routability driven placement.	1
GPL_TIMING_DRIVEN	Specifies whether the placer should use timing driven placement.	1
GUI_TIMING	Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.	1
HOLD_SLACK_MARGIN	Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design’s target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.	0
IO_CONSTRAINTS	File path to the IO constraints .tcl file.
IO_PLACER_H	The metal layer on which to place the I/O pins horizontally (top and bottom of the die).
IO_PLACER_V	The metal layer on which to place the I/O pins vertically (sides of the die).
IR_DROP_LAYER	Default metal layer to report IR drop.
KLAYOUT_TECH_FILE	A mapping from LEF/DEF to GDS using the KLayout tool.
LATCH_MAP_FILE	List of latches treated as a black box by Yosys.
LIB_FILES	A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.
MACRO_BLOCKAGE_HALO	Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.
MACRO_EXTENSION	Sets the number of GCells added to the blockages boundaries from macros.
MACRO_PLACEMENT	Specifies the path of a file on how to place certain macros manually using read_macro_placement.
MACRO_PLACEMENT_TCL	Specifies the path of a TCL file on how to place certain macros manually.
MACRO_PLACE_HALO	Horizontal/vertical halo around macros (microns). Used by automatic macro placement.
MACRO_ROWS_HALO_X	Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.
MACRO_ROWS_HALO_Y	Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.
MACRO_WRAPPERS	The wrapper file that replaces existing macros with their wrapped version.
MAKE_TRACKS	Tcl file that defines add routing tracks to a floorplan.
MATCH_CELL_FOOTPRINT	Enforce sizing operations to only swap cells that have the same layout boundary.	0
MAX_ROUTING_LAYER	The highest metal layer name to be used in routing.
MIN_BUF_CELL_AND_PORTS	Used to insert a buffer cell to pass through wires. Used in synthesis.
MIN_ROUTING_LAYER	The lowest metal layer name to be used in routing.
PDN_TCL	File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.
PLACE_DENSITY	The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread.
PLACE_DENSITY_LB_ADDON	Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.
PLACE_PINS_ARGS	Arguments to place_pins
PLACE_SITE	Placement site for core cells defined in the technology LEF file.
PLATFORM	Specifies process design kit or technology node to be used.
POST_CTS_TCL	Specifies a Tcl script with commands to run after CTS is completed.
PROCESS	Technology node or process in use.
PWR_NETS_VOLTAGES	Used for IR Drop calculation.
RCX_RULES	RC Extraction rules file path.
RECOVER_POWER	Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].	0
REMOVE_ABC_BUFFERS	Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.		yes
REMOVE_CELLS_FOR_EQY	String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.
REPAIR_PDN_VIA_LAYER	Remove power grid vias which generate DRC violations after detailed routing.
REPORT_CLOCK_SKEW	Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.	1
RESYNTH_AREA_RECOVER	Enable re-synthesis for area reclaim.	0
RESYNTH_TIMING_RECOVER	Enable re-synthesis for timing optimization.	0
ROUTING_LAYER_ADJUSTMENT	Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/deltaDebug.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. deltaDebug.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.	0.5
RTLMP_AREA_WT	Weight for the area of the current floorplan.	0.1
RTLMP_ARGS	Overrides all other RTL macro placer arguments.
RTLMP_BOUNDARY_WT	Weight for the boundary or how far the hard macro clusters are from boundaries.	50.0
RTLMP_DEAD_SPACE	Specifies the target dead space percentage, which influences the utilization of a cluster.	0.05
RTLMP_FENCE_LX	Defines the lower left X coordinate for the global fence bounding box in microns.	0.0
RTLMP_FENCE_LY	Defines the lower left Y coordinate for the global fence bounding box in microns.	0.0
RTLMP_FENCE_UX	Defines the upper right X coordinate for the global fence bounding box in microns.	100000000.0
RTLMP_FENCE_UY	Defines the upper right Y coordinate for the global fence bounding box in microns.	100000000.0
RTLMP_MAX_INST	Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.
RTLMP_MAX_LEVEL	Maximum depth of the physical hierarchy tree.	2
RTLMP_MAX_MACRO	Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.
RTLMP_MIN_AR	Specifies the minimum aspect ratio (height/width).	0.33
RTLMP_MIN_INST	Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.
RTLMP_MIN_MACRO	Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.
RTLMP_NOTCH_WT	Weight for the notch, or the existence of dead space that cannot be used for placement and routing.	10.0
RTLMP_OUTLINE_WT	Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.	100.0
RTLMP_RPT_DIR	Path to the directory where reports are saved.
RTLMP_SIGNATURE_NET_THRESHOLD	Minimum number of connections between two clusters to be identified as connected.	50
RTLMP_WIRELENGTH_WT	Weight for half-perimiter wirelength.	100.0
RUN_LOG_NAME_STEM	Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.	run
RUN_SCRIPT	Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.
SC_LEF	Path to technology standard cell LEF file.
SDC_FILE	The path to design constraint (SDC) file.
SDC_GUT	Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.
SEAL_GDS	Seal macro to place around the design.
SETUP_SLACK_MARGIN	Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.	0
SET_RC_TCL	Metal & Via RC definition file path.
SKIP_CTS_REPAIR_TIMING	Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.
SKIP_GATE_CLONING	Do not use gate cloning transform to fix timing violations (default: use gate cloning).
SKIP_INCREMENTAL_REPAIR	Skip incremental repair in global route.	0
SKIP_LAST_GASP	Do not use last gasp optimization to fix timing violations (default: use gate last gasp).
SKIP_PIN_SWAP	Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).
SKIP_REPORT_METRICS	If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.
SLEW_MARGIN	Specifies a slew margin when fixing max slew violations. This option allows you to overfix.
SYNTH_ARGS	Optional synthesis variables for yosys.	-flatten
SYNTH_BLACKBOXES	List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.
SYNTH_GUT	Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.
SYNTH_HIERARCHICAL	Enable to Synthesis hierarchically, otherwise considered flat synthesis.	0
SYNTH_KEEP_MODULES	Mark modules to keep from getting removed in flattening.
SYNTH_MEMORY_MAX_BITS	Maximum number of bits for memory synthesis.	4096
SYNTH_MINIMUM_KEEP_SIZE	For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform’s standard cell library. The default value is platform specific.	0
SYNTH_NETLIST_FILES	Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.
SYNTH_WRAPPED_OPERATORS	Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.
TAPCELL_TCL	Path to Endcap and Welltie cells file.
TAP_CELL_NAME	Name of the cell to use in tap cell insertion.
TECH_LEF	A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.
TIEHI_CELL_AND_PORT	Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.
TIELO_CELL_AND_PORT	Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.
TNS_END_PERCENT	Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.	100
USE_FILL	Whether to perform metal density filling.	0
VERILOG_FILES	The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).
VERILOG_INCLUDE_DIRS	Specifies the include directories for the Verilog input files.
VERILOG_TOP_PARAMS	Apply toplevel params (if exist).
YOSYS_FLAGS	Flags to pass to yosys.	-v 3